1. Field of the Invention
The invention relates to a method of fabricating a high-voltage device that is suitable to apply in a low-voltage device, and more particularly to a method of fabricating a high-voltage device wherein a well formed by ion implantation is used as a drift region.
2. Description of the Related Art
As the size of the device is reduced, the reduced channel length shortens the desired time of the transistor during operation. The problem of short channel effect due to the reduced channel length gradually becomes more serious. According to the formula of electrical field=voltage/length, when the channel length of the transistor is reduced and the voltage is fixed, the energy of the electrons in the channel rises due to the enhancement of the electrical field. On the other hand, the electrical field is also enhanced, raising the energy of the electrons in the channel, when the voltage is increased and the channel length is fixed. Both of these situations may cause electrical breakdown.
For example, devices used for drivers of digital versatile disk (DVD) and liquid crystal display (LCD) need to endure a high voltage of about 12-30V. Generally, a high-voltage device uses an isolation region and a drift region under the isolation region to increase the distance between a source/drain region and a gate, so that the device can be operated normally under a high voltage.
FIGS. 1A-1D are schematic, cross-sectional views of fabrication of a high-voltage device as known in the prior art. Referring to FIG. 1A, an N-type semiconductor substrate (not shown) is provided, and a well 10 having P-type impurity is formed in the semiconductor substrate. A pad oxide layer 20 is formed on the well 10, and a silicon nitride layer 30 is then formed on the pad oxide layer 20.
Referring to FIG. 1B, the silicon nitride layer 30 is patterned by a photoresist layer 40. A portion of the silicon nitride layer 30 is then removed to form a silicon nitride layer 50 on the pad oxide layer 20, and a portion of the well 10 is exposed. N-type ions are implanted into the exposed well 10 to form a drift region 60 having N-type ions.
Referring to FIG. 1C, the photoresist layer 40 is removed. Using the silicon nitride layer 50 as a mask, a field oxide layer 70 with a bird's beak of each side of the silicon nitride layer 50 is grown on the drift region 60. The N-type ions in the drift region 60 are driven in the well 10 at a high temperature to broaden the drift region 60.
Referring to FIG. 1D, the silicon nitride layer 50 and the pad oxide layer 20 are then removed. A thin oxide layer 80 is formed on the well 10 to serve as a gate oxide layer. A polysilicon layer 90 serving as a gate is formed on the well 10 by photolithography. Ion implantation with N-type ions of low dosage and high energy is performed on the well 10, and a drift region 100 having N-type ions is then formed by driven-in thermally. N-type ions having high dosage and low energy are implanted into the well 10 beside the gate 90 to form a source region 110 and a drain region 120.
As shown in FIG. 1D, in order to raise the breakdown voltage of the device, it is necessary to form multiple masks to fabricate the structure of the drift region. Fabrication of masks for the drift region consumes time and money, to the extent that throughput cannot be increased.